BEGIN:VCALENDAR
PRODID:-//Pixl8//Eventfolio//EN
VERSION:2.0
X-WR-TIMEZONE:Europe/London
CALSCALE:GREGORIAN
METHOD:PUBLISH
CLASS:PUBLIC
BEGIN:VTIMEZONE
TZID:Europe/London
LAST-MODIFIED:20260306T231828Z
TZURL:https://www.tzurl.org/zoneinfo-outlook/Europe/London
X-LIC-LOCATION:Europe/London
BEGIN:DAYLIGHT
TZNAME:BST
TZOFFSETFROM:+0000
TZOFFSETTO:+0100
DTSTART:19700329T010000
RRULE:FREQ=YEARLY;BYMONTH=3;BYDAY=-1SU
END:DAYLIGHT
BEGIN:STANDARD
TZNAME:GMT
TZOFFSETFROM:+0100
TZOFFSETTO:+0000
DTSTART:19701025T020000
RRULE:FREQ=YEARLY;BYMONTH=10;BYDAY=-1SU
END:STANDARD
END:VTIMEZONE
BEGIN:VEVENT
DTSTART;TZID=Europe/London:20260804T120000
DTEND;TZID=Europe/London:20260818T020000
DTSTAMP:20260715T151318Z
UID:{C82E170B-6B59-40AC-AA2E22B1232BC7DF}
LOCATION:Online\, Teams
SUMMARY:SystemVerilog Assertions (SVA) for Verification Engineers
DESCRIPTION:An intensive, 3-part hands-on training series in Austin or online designed to master core formal verification strategies, properties, and assertions.\n
 \n
 Event details: https://www.cambridgewireless.co.uk/event-calendar/systemverilog-assertions-sva-for-verification-engineers-1.html
PRIORITY:1
END:VEVENT
END:VCALENDAR