Design for Manufacture Network: "New Challenges in DFT"

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This event will examine the challenges of Test development efficiency in these areas and aims to discuss some of the new approaches and techniques which can be adopted in Product Design and Development and to ease the challenges of DFT in the future.

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About the event

Over the years industry has developed and used a large variety of more or less detailed and more or less formal guidelines for desired and/or mandatory DFT circuit modifications. The common understanding of DFT in the context of Electronic Design Automation (EDA) for modern microelectronics is shaped to a large extent by the capabilities of commercial DFT software tools as well as by the expertise and experience of a professional community of DFT engineers researching, developing, and using such tools. Much of the related body of DFT knowledge focuses on digital circuits while DFT for analog/mixed-signal circuits takes somewhat of a back seat. In addition new manufacturing technologies, such as functional printing, and new materials, such as organic semiconductors, are enabling sophisticated electronic devices to be embedded in everyday objects such as packaging, credit cards, pricing labels, games and clothing. These technologies will produce devices that are truly disposable and as such will have extremely high volumes at produced at extremely low cost generating a whole new set of challenges for the testing industry. This event will examine the challenges of Test development efficiency in these areas and aims to discuss some of the new approaches and techniques which can be adopted in Product Design and Development and to ease the challenges of DFT in the future.

Agenda

09:30 – Regsitration

10:00 – Welcome and Introduction – Patrick McNamee, NMI and Luigi Occhipinti, University of Cambridge

Approaches for the Testing of Large-Area Electronic Devices Manufactured at High Speed and Low Cost – Andrew Flewitt, University of Cambridge

Mixed-Signal DfT – Who’s up to the Challenge?” - Hans Martin von Staudt, Dialog Semiconductor

Verification for Test - Andy White, Nujira

EDT Test Points – The Next Big Thing in Test Compression - Grzegorz Mrugalski, Mentor Graphics

LUNCH

Maximizing Profits with Slack-Based Cell-Aware Test & Diagnostics - Dave Johnson, Synopsys

Riding the 3rd Wave: Reducing Cost of Test for MEMS Sensors – Peter Cockburn, Xcerra

Looking to the Future for DFT and Analogue Test - Peter Sarson, ams

The Potential and Challenges of Concurrent Test – Jean-Francois Lescure, Teradyne

16:00 Close

Event Location

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Location info

Hauser Forum, 3 Babbage Road, Cambridge, CB3 0GT

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