Are you an experienced Front End Digital Design Engineer with at least 5 years’ experience in RTL Design (Preferably Verilog) and experience with ASIC design challenges? This could be the job for you!
What you will be doing as a Digital Design Engineer (ASIC/Verilog/RTL) for our Client:
As a part of this small front end digital design team you will be required to perform a broad array of tasks that will regularly change as the design cycle progresses. The successful candidate will be involved in all aspects of the project lifecycle, from specification to verification and production. Whilst working within this small team you will frequently be interacting with other teams, for instance the back end implementation team, analogue design team and the platform software team. Thus an understanding of these other areas of Software Engineering will be beneficial!
The successful candidate will have 5+ years of experience in RTL design (mostly Verilog) and experience of ASIC design challenges.
Job title and salary will be competitive and based on the candidate’s experience, however our client is seeking the very best and willing to compensate well.
- Experience in Verilog
- Front-end RTL ASIC Design
- Verification Desired:
- System Verilog
- ASIC Synthesis
- Back-end ASIC design experience
- Low Power Design
- Scripting Languages
As a Digital Design Engineer (ASIC/Verlilog/RTL) for our client you would be joining a family of individuals who are passionate about what it is they do and achieve. If you too are passionate and experienced in the field of Digital Design please send your CV today to firstname.lastname@example.org and we’ll get in touch straight away!