IC Senior Digital Design Engineer

Summary

u-blox is a Global fabless semiconductor and modules business operating in three key areas: GNSS positioning, short-range communications systems and Cellular communications systems. We develop IP and full custom ASICs for use within a comprehensive range of chipset and module products.

Seeking a talented and highly skilled front-end ASIC design Engineer with past experience in ground-up development and integration of RTL modules, subsystems and SoCs for Cellular Communication ASICs.  You should be capable of implementing arithmetic and control logic based on own archtectural concepts and by following structures and requriements described by algorthmic models.

You should be committed, curious, creative, innovative, enthusiastic about new technologies, striving for excellence and willing to work in a multi-cultural, International team.

Desired:

  • A Degree in Electrical, Electronics or Computer Engineering - preferably Masters or higher.
  • Proficiency in System Verilog, Verilog and/or VHDL.  (System Verilog Preferred)
  • Experience in commercial HDL design: Embedded CPUs, bus-systems, peripherals, co-processors, memories, clock- and power-management, test and verification.
  • Experience with the implementation of communication systems including DSP, hardware accelerators, co-processors and dedicated IP ideally targeting 3GPP LTE and/or 5G MODEMs.
  • An ability to creatively trade-off frequency, area and power to create highly efficient systems.
  • Experience with C or other embedded software programming language and it's usage for algorithm modelling and verification.
  • Good verbal and written communications skills.
  • Fluency in the English language.
  • Comfortable with travelling to other u-blox design centres across Europe if required

Good to Have:

  • Detailed knowledge of any type of communications standards
  • Experienced with RTL verification methods including UVM and formal methods
  • Experience with mathematical modelling tools e.g. Matlab
  • Experience with FPGA prototyping
  • Experience with ASIC Design for Test methodology
  • Experience with ASIC implementation including Synthesis, SDC and UPF
  • Experience with scripting languages such as Tcl or Python

If this role excites you, we encourage you to apply even if you think you may not meet all the requirements.  We are always looking for outstanding individuals and will provide training if required.

What are your perks?

  • A multicultural and international company with over 50 different nationalities
  • Project-based activities working with colleagues distributed across the globe
  • A start-up and innovation mindset while in the process of scaling-up processes and efficiencies
  • Hybrid working arrangements
  • Spacious office with on-site parking
  • Social activities throughout the year

Office address

u-blox Cambridge Ltd
2nd Floor
Building 2020 Cambourne Business Park
Cambourne
Cambridgeshire
CB23 6DW

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