Summary
As a senior engineer in our team, you will be responsible for ensuring optimal chip testability at die and package level by defining, implementing and verifying the best possible DfT specification according to schedule. In addition you will support the quality department with failure mode and customer returns analysis.
As a senior engineer in our team, you will be responsible for ensuring optimal chip testability at die and package level by defining, implementing and verifying the best possible DfT specification according to schedule. In addition you will support the quality department with failure mode and customer returns analysis.
With your initiative you will have the chance not only to follow, but also to improve our methodology and see your direct impact on the product profitability.
Your Responsibilities
- Meet optimal test coverage and test time
- Test Concept definition and derived Test Specification
- DfT insertion flow (incl. SDC constrains) and pattern generation.
- Design/integrate DfT structures as required in RTL.
- Ensure readiness for production
- Study industrial standards and best practices to improve methodology
- Communication with designers, test and quality engineers
Your Skills and Experience
- Master’s degree in electrical engineering
- >5 years of experience in DfT
- Swiss- or EU-citizen or valid work permit for Switzerland
- Experience in full product life cycle of ASIC Design
- Excellent analytical and problem-solving skills
- Excellent knowledge of Siemens, Cadence, or Synopsys test insertion and ATPG tools
- Excellent knowledge of the IEEE-1149.1 and IEEE-1687 standards
- Experience with at-speed scan testing, and test compression
- Experience integrating DfT features of 3rd party IP
- Experience with memory BIST and logic BIST
- Experience generating test patterns and analysing and debugging test failures
- Experience working with test engineers to implement ATPG vectors on tester hardware
- Proficiency in HDL (VHDL/Verilog)
- Proficiency in scripting languages such as Tcl, Python or Perl
Bonus Point
- C++ knowledge
- Automated Test Equipment (ATE) knowledge (e.g. ADVANTEST, LTX)
- Experience in Synthesis, SDC timing constraints and Static Timing Analysis
What are your perks?
- A multicultural and international company with over 50 different nationalities
- Project-based activities working with colleagues distributed across the globe
- A start-up and innovation mindset while in the process of scaling-up processes and efficiencies
- Hybrid work model (40% remote/60% office) & flexible working hours
- Training and career growth opportunities
- Company Bonus and Stock Option Plan
Office address
u-blox Cambridge Ltd
2nd Floor
Building 2020 Cambourne Business Park
Cambourne
Cambridgeshire
CB23 6DW
