As a Senior “Middle End” design Engineer, you will be a key team member responsible for the Synthesis and Static Timing Analysis of large-scale, complex SoCs for u-blox IoT and Positioning products. You will develop and improve Synthesis methodology and flow using the Tcl scripting language and define all timing constraints (SDC) and power intent (UPF). Prior experience with the Cadence Genus and Tempus tools is highly desirable.
You will work closely with both the RTL design and back-end implementation teams to ensure high quality production-ready SoC implementations in Industry-leading technology nodes.
High energy candidates with strong communication skills will thrive in our varied and exciting multi-national work environment.
- Responsible for state-of-the-art RTL-to-netlist synthesis methodology and flow
- Responsible for SDC and UPF constraints
- Responsible for achieving best possible performance/power/area trade-off for multi-million gate ASICs within project schedules
- Clear, concise communication skills with an ability to efficiently drive decisions
- Strong proficiency in written communication
- Excellent analytical and problem-solving skills
- An ability to work independently and as part of a team
- Strong mindset for innovation and automation
Candidates should have experience in most of the following:
- Deep understanding of synthesis and timing methodologies including physical synthesis and definitions for MMMC and OCV
- Excellent knowledge of timing and power constraints (SDC+UPF)
- Competence with Static Timing Analysis (e.g. Tempus) and SDC validation tools (e.g., Excellicon, Litmus, Fishtail) to validate timing constraints
- Familiarity with Logical Equivalence Checking (LEC)
- Power intent verification (CLP)
- RTL input checks (LINT, DFT, CDC, RDC)
- Proficiency in Tcl scripting
- Master’s degree in Electrical Engineering
- At least 5 years of experience in a middle-end and synthesis role
- Fluent in English
Building 2020 Cambourne Business Park