Summary
ASIC Design Engineer, working in Digital Design Team based in Cambridge, contributes to development of CPU based subsystems and provides support for DSP integration. Duties include RTL development, micro-architectural explorations through synthesis and power estimation and verification. This role will be primarily focused on development of Qualcomms class leading Audio SoCs for next generation audio platforms.
Qualcomm is a company of inventors that unlocked 5G ushering in an age of rapid acceleration in connectivity and new possibilities that will transform industries, create jobs, and enrich lives. But this is just the beginning. It takes inventive minds with diverse skills, backgrounds, and cultures to transform 5Gs potential into world-changing technologies and products. This is the Invention Age and this is where you come in.
Minimum Qulaifications:
- A degree (or higher qualification) in math/science/electronics
- Knowledgeable in CPU and CPU-based-subsystem architecture/design
- 5 to 10 years hands-on experience in ASIC implementation : RTL, Synthesis, LINT, CDC
- Fluency in hardware description languages (Verilog/SV)
- Good understanding of verification techniques
- Familiarity with physical synthesis flow
- Good communications skills. Must be able to articulate design ideas, both verbally and in written form
- References to a number of years experience are for indicative purposes only. Applications from candidates with equivalent experience will be considered, provided that the candidate can demonstrate an ability to fulfil the principal duties of the role and possesses the required competencies.
Perfered Qualifications:
- Experience of DSP hardware/software development and optimization
- Experience of FPGA platforms
- Knowledge of scripting languages (e.g. python, shell) and EDA tools (for simulation, synthesis, Lint-ing)
- Knowledge of PTPX and PowerArtist power estimation tools
Education requirements:
- A degree (or higher qualification) in math/science/electronics
Keywords:
SoC, ASIC, RTL, DFT, IoT ASIC/SoC design, Computer Architecture, DSP, Power estimation, Critical path optimization
