AMS Co-Simulation (RNM & UVM)

AMS Co-Simulation (RNM & UVM)

🎟 Cambridge Wireless members can get 20% discount by using the code: Cw20%Dc


Learn how modern mixed-signal verification environments integrate SystemVerilog, Verilog-AMS, SPICE, Real Number Modeling (RNM), and UVM methodologies. This live, online 3-part training series focuses on real-number modeling and UVM-based AMS co-simulation methods for engineering teams that need scalable mixed-signal verification flows and faster execution speeds.


👥 Who Should Attend:

• Design Verification (DV) Engineers

• AMS & Mixed-Signal Engineers

• UVM Verification Engineers & RTL Engineers moving into AMS

• Verification Leads & Architects


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📚 SERIES BREAKDOWN:

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🔹 Part 1: AMS Co-Simulation Fundamentals

📅 Tuesday, 4 August 2026 | 14:30 - 16:30 BST

Learn the foundations of AMS co-simulation and how digital and analog simulation engines synchronize. Covers event-driven vs continuous-time simulation, Verilog-AMS/Verilog-A syntax, and SPICE basics for digital engineers.

👉 [Click here to register for Part 1]


🔹 Part 2: Compilation, Power & RNM

📅 Tuesday, 11 August 2026 | 14:30 - 16:30 BST

Explore AMS compilation flows, power-aware verification concepts, and Real Number Modeling techniques for faster simulations. Covers VCS-AD flows, connect modules, nettype real, and resolution functions.

👉 [Click here to register for Part 2]


🔹 Part 3: UVM Integration & Debug

📅 Tuesday, 18 August 2026 | 14:30 - 16:30 BST

Apply advanced UVM methodologies to mixed-signal verification environments. Covers UVM-AMS testbench architecture, RNM testbench integration, mixed-signal FSDB generation, and Verdi AMS debugging.

👉 [Click here to register for Part 3]


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💡 Key Takeaways across the Series:

• Understand AMS co-simulation architectures and analog/digital engine synchronization.

• Learn how to apply Real Number Modeling (RNM) using SystemVerilog nettypes for faster simulation execution.

• Integrate UVM testbench structures (drivers, monitors, and interfaces) with analog and mixed-signal blocks.

• Master practical mixed-signal debugging workflows, FSDB generation, and convergence analysis in Verdi.


💰 Pricing & Bundles:

• Single Part Ticket: $60 (or $48 with code Cw20%Dc)

• Complete Series Bundle (All 3 Parts): $150 (Be sure to apply code Cw20%Dc at checkout for an extra 20% off)


Format: Live Online (Microsoft Teams)

Duration: 3 Days Total | 2 Hours per Day (2:30 PM - 4:30 PM BST)