🎟️ Cambridge Wireless members can get 20% discount by using the code: Cw20%Dc

Step into the future of verification with this AI in Design Verification Hands-on Training — a highly interactive, full-day experience where engineers build, test, and experiment with AI-driven DV workflows in real time. 

Rather than traditional training, participants will apply Generative AI, Machine Learning, and Reinforcement Learning techniques to solve practical verification challenges — from automated UVM generation to intelligent debug and coverage optimization. Guided by expert mentors, this training is designed to help you move from theory to real implementation in a single day.

🛠️ Hands-on Training Challenges Include:

• Generating UVM components from specifications using LLMs.

• Automating testbench creation with AI assistance.

• Applying ML techniques to log analysis and coverage prediction.

• Using RL / Genetic Algorithms for intelligent test generation.

• Improving coverage closure using AI-driven insights.

• Debugging failing designs with AI-assisted workflows.

👥 Who Should Join:

• Design Verification engineers (SystemVerilog / UVM)

• RTL and SoC engineers exploring AI-driven workflows.

• Technical leads evaluating AI adoption in DV.

• Engineers looking to boost productivity and reduce manual effort.

⚠️ Note: This session is limited to 12 participants to ensure a highly interactive, high-impact experience with direct expert support. It will be recorded and made available to all registrants 1 week post-session.

Format: Hybrid (In-person at San Jose, CA or Live Online)

Duration: Full-Day Training (12:00 PM - 7:00 PM PDT)

To secure your spot, please register on our ticket page:

👉    [Click here to register on Ticket Tailor]