Join Alpinum Consulting for an intensive, hands-on 3-part online training series designed for RTL design, verification, and embedded systems engineers. This series scales from initial block-level debugging up to complex, full-system SoC verification and validation.

🗓️ Course Schedule & Registration Links:

• Part 1: Block-Level RTL Debug (12 - 13 Oct 2026, 12:00 - 16:00 BST)

  Focuses on interactive simulation, waveform analysis, and root-causing bugs within standalone IP blocks.

  👉  [Click here to register for Part 1]

• Part 2: CPU HW/SW Debug (14 - 15 Oct 2026, 12:00 - 16:00 BST)

  Focuses on processor cores, pipeline debugging, hardware/software co-verification, and assembly/C-level debugging.

  👉   [Click here to register for Part 2]

• Part 3: SoC HW & HW/SW Debug (19 - 20 Oct 2026, 12:00 - 16:00 BST)

  Focuses on full System-on-Chip architecture, JTAG infrastructure, multi-core debug trace, and post-silicon validation.

  👉   [Click here to register for Part 3]

💰 Pricing:

• Individual Part Ticket: $60 per part

• Full Series Bundle Ticket: $150 (Save $30)