🎟 Cambridge Wireless members can get 20% discount by using the code: Cw20%Dc

Learn how to build robust assertion-based verification methodologies using SystemVerilog Assertions (SVA), simulation, and formal verification workflows in this live online training series. Designed for verification engineers working with RTL design, simulation, and formal environments, this 3-part intensive series focuses on mastering syntax, temporal properties, and real-design verification strategies.

👥 Who Should Attend:

• Verification & Design Verification (DV) Engineers

• FPGA and ASIC Engineers

• RTL Designers

• Formal Verification Engineers & Semiconductor Professionals

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📚 SERIES BREAKDOWN:

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🔹 Part 1: Foundations & Introduction to SVA

📅 Tuesday, 4 August 2026 | 12:00 - 14:00 BST

Learn the fundamentals of Assertion-Based Verification (ABV) and SystemVerilog Assertions (SVA). This session covers immediate vs. concurrent assertions, SVA syntax, scheduling concepts, implication operators, built-in functions, and a practical FIFO worked example with a live VCS demonstration.

🔹 Part 2: Advanced Properties, Sequences & Auxiliary Logic

📅 Tuesday, 11 August 2026 | 12:00 - 14:00 BST

Explore advanced SVA constructs, property semantics, and auxiliary logic techniques. Deep dive into vacuous success, timing windows, sequence repetition and combination operators, mutex/race conditions, and live VC Formal/Jasper Gold workflow demonstrations.

🔹 Part 3: SVA Reuse, Formal Signoff & RISC-V Case Study

📅 Tuesday, 18 August 2026 | 12:00 - 14:00 BST

Learn to scale SVA across simulation and formal signoff flows. Covers local variables, FIFO specification quality, formal verification metrics, and signoff methodologies (QOFV). Features a comprehensive RISC-V CPU verification case study using industrial formal tools.

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💡 Key Takeaways across the Series:

• Understand SVA syntax, semantics, and timing behavior.

• Write reusable, parameterised assertions and properties for complex digital designs.

• Implement auxiliary helper logic to monitor complex interface protocols.

• Analyze formal coverage metrics and execute structured formal signoff.

• Apply SVA techniques to real-world FIFO, ALU, and RISC-V processor pipelines.

💰 Pricing & Bundles:

• Single Part Ticket: $25 (or $20 with code Cw20%Dc)

• Complete Series Bundle (All 3 Parts): $60 (Be sure to apply code Cw20%Dc at checkout for an extra 20% off)

Format: Live Online (Microsoft Teams)

Duration: 3 Days Total | 2 Hours per Day (12:00 PM - 2:00 PM BST)