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UVM Verification Engineer

Summary

A leading technology client has a number of contracts available for UVM Verification Engineers.

My client is looking for freelancers with extensive experience of architecting and implementing Verification test benches for complex IP & module level design.

Duration: 6 Month rolling

Start date: ASAP

Location: Cambridge

Number of openings: 3

Hourly rate: £45-£48

DOE Key skills required for the UVM Verification Engineer:

  • Expert in System Verilog and UVM Methodology
  • Experience in Video, GPU, Display Verification

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