Summary
Are you an expert digital design verification engineer with 15+ years experience developing mixed-signal chips? Do you want to play a key role in building next generation Wi-Fi chips that will truly enable the Internet of Things? Keen to make a real difference in a VC-backed high growth company while working in a dynamic & fun environment? Then join Morse Micro, Australia’s largest fabless semiconductor company! We opened our Cambridge office in January 2022 and are looking for the brightest of the brightest to join us in the The Bradfield Centre in the Cambridge Science Park.
Your role will be within the digital team and involve design and verification of our chips. Our ideal candidate will be very experienced in both design and verification of mixed signal chips. Applicants will need to be experienced with designing and verifying complex, mixed-signal SoCs. You will be responsible for the design, development, and verification of digital subsystems within our chips. Additional tasks will involve managing continuous integration (CI) regression testing flows, evaluating existing test suites and expanding in areas where needed and running and debugging power aware and gate level simulations.
Responsibilities include:
- Chip and block-level design verification
- Enhancement of our verification infrastructure and methods
- Support of chip team’s verification efforts through to tapeout
- Planing, tracking and documentation of verification throughout chip development project
- Delivery of large complex projects on time
- Running lint checks
- Mentoring of junior team members
- Providing overall technical expertise and brilliance
What we’re looking for:
- 15+ years relevant industry experience
- MSc in Electrical / Electronics / Communication Engineering or Computer Science
- A deep understanding of digital design verification fundamentals including low power and multi-clock-domain design for mass-produced, mixed-signal chips
- Willing to think outside of the standard industry approaches
- Expert in digital simulation, some experience with design and AMS simulation
- Very experienced with the Cadence or Synopsys simulation suites
- Experience with coverage collection tools
- Experience defining functional verification requirements, implementing tests to meet them
- Expert in HDL languages such as Verilog, SystemVerilog or VHDL
- Experience with building complex testbench infrastructures
- Experience running and debugging gate level simulations in post-PnR netlists with SDF annotation, power-aware simulation experience is a plus
- Experience setting up and maintaining continuous integration (CI) flows for regression testing and reporting status
- A good understanding of embedded processor systems, familiarity with RISC-V is a plus
- Experience writing embedded C and structuring code in a way which makes reusability and maintenance a breeze
- Experience with cocotb is a plus
- Hands-on experience with Linux development environment staples such as make, shell scripts and Python
- Experience using the git revision control tool
What we offer:
- Competitive salary + excellent stock option package
- Ability to work alongside some of the world's best engineers in a fast-paced environment and make a real impact
- Work trips to Morse Micro HQ in Australia!
Who we are:
Morse Micro is a fabless semiconductor company building Wi-Fi HaLow (802.11ah) chips for the Internet of Things (IoT). We are a team of wireless experts that love to innovate and invent. Together, we are building the world’s lowest power Wi-Fi technology that will enable billions of IoT devices to connect securely to the internet. We are a global team with offices in Sydney & Picton (Australia), Irvine & Boston (USA), Cambridge (UK) and Hangzhou (China).
